Output capacitance extraction of p-GaN HEMTs under multi pulse switching across variable frequencies and drain-bias stress

This study proposes a method to extract the output capacitance (COSS) of 200 V Schottky p-GaN HEMTs under multi-pulse switching conditions. By employing a gate-source shorted configuration, both CGD and CDS are captured during switching transients. To minimize ringing oscillations, a four layer printed circuit board (PCB) with low parasitic inductance was designed, along with a top-cooled heat sink to enhance thermal management. The results under various switching frequencies and off-state VDS biases reveal that COSS variations arise from the combined effects of VDS-induced electron trapping during the off-state and hole injection during reverse conduction. The extraction method and findings contribute to the accurate evaluation of COSS in multi-pulse switching applications and aid in the design of power converters and the switching performance prediction of GaN power devices.

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