Pang, Wai Leong (2003) Development Of An 8-Bit Fpga-Based Asynchronous Risc Pipelined Processor For Data Encryption. Masters thesis, Universiti Putra Malaysia.
Microprocessors are widely used in various applications. One of the application is in the area of data security where data are encrypted and decrypted before and after transfer via communication channel. The microprocessor design can be categorized into two types, which are synchronous and asynchronous processors. The asynchronous processor may offer better speed improvement because it is self-timed where a control circuit will generate enable signals for all instruction executions based on the request and acknowledgement signals. Unlike the asynchronous design, synchronous design requires global clock. The clock must be long enough to accommodate the worst-case delay. In this work, an 8-bit asynchronous processor is designed based on a synchronous RISC pipe lined processor architecture. The synchronous processor consists of three stages. They are instruction fetch stage, instruction decode stage and execution stage. The reduce instruction set computer (RISC) architecture is used to minimize the instruction and to perform specific operation. To design the asynchronous processor, an asynchronous control circuit is added to synchronous design. The asynchronous control circuit is designed based on handshake protocol. Both the synchronous and asynchronous designs are applied fully using VHDL. The MAX+PLUS II is used as the simulation tools to design and for design verification. The UP1 education board that contains the FLEX10K chip is used to observe the hardware operation. The asynchronous processor was successfully designed with higher million instructions per second (MIPS) and higher operation frequency as compared to synchronous processor. The asynchronous processor has 10.772 MIPS and operated under frequency of 11. 16MHz. The asynchronous processor design consumed 63% of the total logic cells in FLEX10K chip. The processor fits in FLEX10K and provides extra spaces for future expansion.
|Item Type:||Thesis (Masters)|
|Subject:||Asynchronous transfer mode|
|Chairman Supervisor:||Roslina Mohd. Sidek, PhD|
|Call Number:||FK 2003 49|
|Faculty or Institute:||Faculty of Engineering|
|Deposited By:||Mohd Nezeri Mohamad|
|Deposited On:||14 Jul 2011 05:09|
|Last Modified:||14 Jul 2011 05:09|
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