Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology

Alihasan, Wael A. Y. (2009) Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology. Masters thesis, Universiti Putra Malaysia.

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Abstract

Over the last two decade, digital signal processing (DSP) has grown rapidly in electronic systems to provide more reconfigureability and programmability in the applications, compared to analog component, which allows easier design and test automation. Digital circuit usage is increasing because of scaling properties of very large scale integration (VLSI) processes. This has allowed new generation of digital circuit to attain higher speed, more functionality per chip, low power dissipation, lower cost. Analog world, analog to digital converter (ADC) are used to convert the signal from analog to digital domain. For interfacing with DSP sample and hold (S/H) circuit is a key building block in, and is often used in front end of the ADCs to relax their timing requirement. The function of S/H circuit is to take samples to its input signal and hold these samples in its output for some period of time. The analog circuits in low voltage and low power have assumed great significance due to mixed-mode design required for modern electronic gadgets that demand portability and little power consumption. The mixed mode circuit has existence of both analog and digital circuits on the same chip and it is possible to have low voltage digital circuit in modern scaled-down technologies. However the same is not always true with analog circuits due to the constrains of device noise level and threshold voltage (VT) of MOSFET. Thus for analog circuit to co-exist on the same substrate along with digital system and share same supply voltage, the operation of analog circuit in low voltage environment is essential. The objective of this research is to design a low-voltage, high-performance S/H circuit that will address the above problems. A typical switch capacitor S/H circuit needs amplifier, switches and capacitor. New amplifier have been designed by using the architecture of single stage fully differential folded cascode low voltage operation transconductance amplifier (OTA) which has high gain and speed; the gin boosting technique was used for purpose of increasing the gain of the OTA. This technique does not affect the speed of the single stage. The transmission gate switches using CMOS devices, which have higher linearity and higher speed over a single MOS switch, have been designed for use in the S/H circuit. The switches are operated by clock generator with two non overlapping clock signals having low rise and fall time offering low noise for the S/H circuit. The clock was designed with 77.17ps rise and fall time to reduce the errors of driving MOS switches which results in higher linearity. The S/H circuit was designed to operate with 1.8V supply voltage in 0.18um technology. The sampling rate is 40MSPS with spurious free dynamic range (SFDR) 65.7dB and SNR 70dB.

Item Type:Thesis (Masters)
Chairman Supervisor:Professor Sudhanshu Shekhar Jamuar
Call Number:FK 2009 47
Faculty or Institute:Faculty of Engineering
ID Code:7357
Deposited By: Muizzudin Kaspol
Deposited On:16 Jun 2010 07:27
Last Modified:27 May 2013 07:34

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