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Sub-picosecond jitter resolution wide range digital delay line for SoC integration

Abdulrazzaq, Bilal Isam and Abdul Halin, Izhal and Mohd Sidek, Roslina and Shafie, Suhaidi and Md Yunus, Nurul Amziah and Kawahito, Shoji (2015) Sub-picosecond jitter resolution wide range digital delay line for SoC integration. In: 2015 IEEE International Circuits and Systems Symposium (ICSyS 2015), 2-4 Sept. 2015, Holiday Villa Beach Resort & Spa, Langkawi, Kedah. pp. 44-48.

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Abstract

A novel three-stage architecture programmable digital delay line (DDL) with a picosecond resolution, 1μs range, and sub-picosecond jitter performance is proposed. Through circuit simulation, a dynamic range of 1μs is obtained in the first stage using 10-bit counters operating at a frequency of 1 GHz. The second stage further refines the delay to 23ps using a tapped inverter chain architecture. Finally, the third stage constructed using a DLL with NAND gate based delay elements further refines the delay step to 1ps resolution with a 0.1ps RMS jitter performance. The proposed digital delay line is designed using a standard 0.13μm Silterra CMOS technology.

Item Type:Conference or Workshop Item (Paper)
Keyword:Delay element; Delay step; Delay-locked loop (DLL); Digital delay line; Dynamic range; Inverter; Jitter; SoC
Faculty or Institute:Faculty of Engineering
Publisher:IEEE
DOI Number:10.1109/CircuitsAndSystems.2015.7394062
Altmetrics:http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/CircuitsAndSystems.2015.7394062
ID Code:55971
Deposited By: Nabilah Mustapa
Deposited On:03 Jul 2017 17:25
Last Modified:03 Jul 2017 17:25

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