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A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability

Abdulrazzaq, Bilal Isam and Abdul Halin, Izhal and Lee, Lini and Mohd Sidek, Roslina and Md Yunus, Nurul Amziah (2017) A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability. Pertanika Journal of Science & Technology, 25 (spec. Feb.). pp. 123-132. ISSN 0128-7680; ESSN: 2231-8526

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Abstract

A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2µs delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous latches has significantly reduced the large occupied active silicon area as well as the huge power consumption. The generated coarse time delay has shown excellent linearity and immunity to PVT variations. The proposed CMOS delay line is designed using a standard 0.13µm Silterra CMOS technology. The active layout area is (101 x 142) µm2, and the total power consumption is only 0.1 µW.

Item Type:Article
Keyword:CMOS delay line; Synchronous counter; Latches; Delay element; Delay range; Duty cycle; Linearity; PVT variations
Faculty or Institute:Faculty of Engineering
Publisher:Universiti Putra Malaysia Press
ID Code:55852
Deposited By: Nabilah Mustapa
Deposited On:30 Jun 2017 17:47
Last Modified:05 Jul 2017 11:44

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