Kooh, Roy Jinn Chye (2000) Device Characterization of 0.8-µm CMOS Technology. Masters thesis, Universiti Putra Malaysia.
The development of the O.8-um CMOS technology was carried out in Mimos Berhad and is considered to be the first in-house development to be done in Malaysia. In every technology development, characterization of the technology is always necessary to gauge its performance and reliability. This thesis is a result of such work and the emphasis of the characterization is the devices of O.8-um CMOS technology. The main work of this thesis includes the effort taken to understand the technology, the design of test structures and the development of test methodology to qualify the O. 8-um CMOS technology. The test structures design includes the p-n junction, MOS enhancement transistor, thick oxide transistor and MOS capacitor. The p-n junction was designed specifically to investigate the breakdown voltage of the source/drain of NMOS and PMOS, which is a very important parameter in determining the reliability of the devices. MOS enhancement transistor characteristics were examined in detail with the NMOS and PMOS test structures. Typical I-V characteristics and some important device parameters were obtained from the I-V characterization. Two main issues, i.e. threshold voltage variation and off state leakage current were discussed in detail. Test methodologies for effective channel length determination (LEFF), Drain-Induced Barrier Lowering (DIBL), punchthrough and Gate-Induced Drain Leakage (GIDL) are among the important ones that were developed. The isolation issues for the devices were addressed using the thick oxide transistors to obtain the high field threshold voltage (VTF). The VIP is used as a measure to show the absence of parasitic FET near the operating voltage of 5V. The conventional MOS capacitor was also included as one of the test structures due to its simplicity and enormous amount of information that can be obtained. A detail capacitance-voltage (C-V) characterization was carried out using the Simultaneous Feedback Charge technique. Analysis includes the extraction of doping profiles, interface trap density (Dit) and some process information such as conductivity and gate oxide thickness (tox). The work has shown a tremendous effort being put to design test structures and characterize the O.8-um CMOS devices. The test structures which designs are based on its predecessor, the 1.0-um CMOS technology test structures, have proven to be reliable and capable. Based on the result analysis, it shows that the O.8-um CMOS devices have achieved a creditable performance and reliability. As a conclusion, this work have achieved its objective to design device test structures, develop the respective test methodology and to characterize the technology.
|Item Type:||Thesis (Masters)|
|Subject:||Metal oxide semiconductors, Complementary|
|Subject:||Integrated circuits - Very large scale integration|
|Chairman Supervisor:||Dr. Bambang Sunaryo Suparjo, PhD|
|Call Number:||FK 2000 45|
|Faculty or Institute:||Faculty of Engineering|
|Deposited By:||Nur Kamila Ramli|
|Deposited On:||04 May 2011 03:10|
|Last Modified:||04 May 2011 03:11|
Repository Staff Only: Edit item detail
Document Download Statistics
This item has been downloaded for since 04 May 2011 03:10.